The project involved integrating two serial peripheral modules, Serial Peripheral Interface SPI and Universal Asynchronous Receiver Transmitter UART, into the UETRVPCore. This intricate process required careful amendments to the existing RTL codes of SPI and UART modules with the newly modified codes, aligning them with the constraints of the UETRVPCore to ensure proper functionality. Vivado was employed to simulate and verify these integrated modules, and successful synthesis and implementation confirmed their correctness. Concurrently, a sophisticated C code file was developed to run and test the modules, contributing to the comprehensive validation process. This task not only enhanced proficiency in hardware description languages and synthesis tools but also demonstrated the capability to seamlessly integrate and validate complex systems within the specified constraints.